az10e111 az100e111 ecl/pecl 1:9 differential clock driver 1630 s. stapley dr., suite 125 ? mesa, arizona 85204 ? usa ? (480) 962-5881 ? fax (480) 890-2541 www.azmicrotek.com arizona microtek, inc. features ? low skew ? differential design ? clock enable ? v bb output ? operating range of 4.2v to 5.46v ? 75k ? internal input pulldown resistors ? direct replacement for on semiconductor mc10e111 & mc100e111 description the az10/100e111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. the in signal is fanned-out to nine identical differential outputs. an enable input is also provided. a high disables the device by forcing all q outputs low and all q outputs high. the az100e111 provides a v bb output for single-ended use or a dc bias reference for ac coupling to the device. for single?ended input applications, the v bb reference should be connected to one side of the in/in differential input pair. the input signa l is then fed to the other in/in input. the v bb pin should be used only as a bias for the e111 as its sink/source capability is limited. when used, the v bb pin should be bypassed to ground via a 0.01 f capacitor. the device is specifically designed, modeled and produced with low skew as the key goal. optimal design and layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent t pd distributions from lot-to-lot. the net result is a dependable, low skew device. to ensure that the tight skew specification is met, both sides of the differential output must be terminated into 50 ? , even if only one side is used. in most applications all nine differential pairs will be used and therefore terminated. in the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on the same package side (i.e. sharing the same v cco ) as the pair(s) being used on that side, in order to maintain minimum skew. failure to do this will result in small degr adations of propagation delay (on the order of 10-20ps) of the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin. note: specifications in the ecl/pecl tables are valid when thermal equilibrium is established. package availability package part no. marking plcc 28 az10e111fn azm10e111 plcc 28 t&r az10e111fnr2 azm10e111 plcc 28 AZ100E111FN azm100e111 plcc 28 t&r AZ100E111FNr2 azm100e111
az10e111 az100e111 october 2001 * rev - 2 www.azmicrotek.com 2 absolute maximum ratings are those values beyond which device life may be impaired. symbol characteristic rating unit v cc pecl power supply (v ee = 0v) 0 to +8.0 vdc v i pecl input voltage (v ee = 0v) 0 to +6.0 vdc v ee ecl power supply (v cc = 0v) -8.0 to 0 vdc v i ecl input voltage (v cc = 0v) -6.0 to 0 vdc i out output current --- continuous --- surge 50 100 ma t a operating temperature range -40 to +85 c t stg storage temperature range -65 to +150 c 10k ecl dc characteristics (v ee = -4.94v to -5.46v, v cc = v cco = gnd) -40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit v oh output high voltage 1 -1080 -890 -1020 -840 -980 -810 -910 -720 mv v ol output low voltage 1 -1950 -1650 -1950 -1630 -1950 -1630 -1950 -1595 mv v ih input high voltage -1230 -890 -1170 -840 -1130 -810 -1060 -720 mv v il input low voltage -1950 -1500 -1950 -1480 -1950 -1480 -1950 -1445 mv v bb reference voltage -1430 -1300 -1380 -1270 -1350 -1250 -1310 -1190 mv i ih input high current 150 150 150 150 a i il input low current 0.5 0.5 0.5 0.5 a i ee power supply current 48 60 48 60 48 60 48 60 ma 1. each output is terminated through a 50 ? resistor to v cc ? 2v. logic symbol v bb in in en q0 q0 q1 q1 q2 q2 q3 q3 q4 q4 q5 q5 q6 q6 q7 q7 q8 q8 26 27 28 1 2 3 4 q0 q0 q1 q2 v cco q1 q2 q3 q3 v cc q5 v cco q5 q6 q6 q7 v cco q8 q8 v ee in nc 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 v bb in en q4 q4 q7 pinout: 28-lead plcc (top view) pin description pin function in, in differential input pair en enable q0, q0 - q8, q8 differential outputs v bb v bb output v cc , v cco positive supply v ee negative supply
az10e111 az100e111 october 2001 * rev - 2 www.azmicrotek.com 3 10k pecl dc characteristics (v ee = gnd, v cc = v cco = +5.0v) -40 c 0 c 25 c 85 c symbol characteristic min t yp max min t yp max min t yp max min t yp max unit v oh output high voltage 1,2 3920 4110 3980 4160 4020 4190 4090 4280 mv v ol output low voltage 1,2 3050 3350 3050 3370 3050 3370 3050 3405 mv v ih input high voltage 1 3770 4110 3830 4160 3870 4190 3940 4280 mv v il input low voltage 1 3050 3500 3050 3520 3050 3520 3050 3555 mv v bb reference voltage 1 3570 3700 3620 3730 3650 3750 3690 3810 mv i ih input high current 150 150 150 150 a i il input low current 0.5 0.5 0.5 0.5 a i ee power supply current 48 60 48 60 48 60 48 60 ma 1. for supply voltages other that 5.0v, use the ecl table values and add supply voltage value. 2. each output is terminated through a 50 ? resistor to v cc ? 2v. 100k ecl dc characteristics (v ee = -4.2v to -5.46v, v cc = v cco = gnd) -40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit v oh output high voltage 1 -1085 -1005 -880 -1025 -955 -880 -1025 -955 -880 -1025 -955 -880 mv v ol output low voltage 1 -1830 -1695 -1555 -1810 -1705 -1620 -1810 -1705 -1620 -1810 -1705 -1620 mv v ih input high voltage -1165 -880 -1165 -880 -1165 -880 -1165 -880 mv v il input low voltage -1810 -1475 -1810 -1475 -1810 -1475 -1810 -1475 mv v bb reference voltage -1380 -1260 -1380 -1260 -1380 -1260 -1380 -1260 mv i ih input high current 150 150 150 150 a i il input low current 0.5 0.5 0.5 0.5 a i ee power supply current 48 60 48 60 48 60 55 69 ma 1. each output is terminated through a 50 ? resistor to v cc ? 2v. 100k pecl dc characteristics (v ee = gnd, v cc = v cco = +5.0v) -40 c 0 c 25 c 85 c symbol characteristic min t yp max min t yp max min t yp max min t yp max unit v oh output high voltage 1,2 3915 3995 4120 3975 4045 4120 3975 4045 4120 3975 4045 4120 mv v ol output low voltage 1,2 3170 3305 3445 3190 3295 3380 3190 3295 3380 3190 3295 3380 mv v ih input high voltage 1 3835 4120 3835 4120 3835 4120 3835 4120 mv v il input low voltage 1 3190 3525 3190 3525 3190 3525 3190 3525 mv v bb reference voltage 1 3620 3740 3620 3740 3620 3740 3620 3740 mv i ih input high current 150 150 150 150 a i il input low current 0.5 0.5 0.5 0.5 a i ee power supply current 48 60 48 60 48 60 55 69 ma 1. for supply voltages other that 5.0v, use the ecl table values and add supply voltage value. 2. each output is terminated through a 50 ? resistor to v cc ? 2v.
az10e111 az100e111 october 2001 * rev - 2 www.azmicrotek.com 4 ac characteristics (v ee =10e(-4.94v to -5.46v), 100e(-4.2v to -5.46v); v cc =v cco =gnd or v ee =gnd; v cc =v cco = 10e(+4.94v to +5.46v), 100e(+4.2v to +5.46v) ) -40 c 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max min typ max unit t plh / t phl propagation delay to output in (diff) 1 in (se) 2 enable 3 disable 3 380 280 400 400 680 780 900 900 460 410 450 450 560 610 850 850 480 430 450 450 580 630 850 850 510 460 450 450 610 660 850 850 ps t s setup time en to in 5 250 0 200 0 200 0 200 0 ps t h hold time in to en 6 50 -200 0 -200 0 -200 0 -200 ps t r release time en to in 7 350 100 300 100 300 100 300 100 ps t skew within-device skew 4 25 75 25 50 25 50 25 50 ps v pp (ac) minimum input swing 8 250 250 250 250 mv v cmr common mode range 9 v cc - 1.6 v cc - 0.4 v cc - 1.6 v cc - 0.4 v cc - 1.6 v cc - 0.4 v cc - 1.6 v cc - 0.4 v t r / t f rise/fall time 250 650 275 600 275 600 275 600 ps 1. the differential propagation delay is de fined as the delay from the crossing point s of the differential input signals to th e crossing point of the differential output signals. 2. the single-ended propagation delay is de fined as the delay from the 50% point of the input signal to th e 50% point of the o utput signal. 3. enable is defined as the propagation delay from the 50% point of a negative transition on en to the 50% point of a po sitive transition on q (or a negative transition on q ). disable is defined as the propagation delay from the 50% point of a positive transition on en to the 50% point of a negative transition on q (or a positive transition on q ). 4. the within-device skew is defined as the worst-case difference between any two si milar delay paths within a single device. 5. the setup time is the minimum time that en must be asserted prior to the next transition of in/ in to prevent an output response greater than 75mv to that in/ in transition (see figure 1). 6. the hold time is the minimum time that en must remain asserted after a negative going in or a positive going in to prevent an output response greater than 75 mv to that in/ in transition (see figure 2). 7. the release time is the minimum time that en must be de-asserted prior to the next in/ in transition to ensure an output response that meets the specified in to q propagation delay a nd output transition times (see figure 3). 8. v pp (min) is defined as the minimum peak-to-peak input differentia l voltage which will cause no incr ease in the propagation delay. the v pp (min) is ac limited for the e111, because differential input as low as 50 mv will still produce full ecl levels at the output. 9. v cmr is defined as the range within which the v ih level may vary, with the device still meetin g the propagation delay specification. the v il level must be such that the peak-to- peak voltage is less than 1.0v and greater than or equal to v pp (min). in in en h in in en in in en
az10e111 az100e111 october 2001 * rev - 2 www.azmicrotek.com 5 package diagram plcc 28 millimeters inches dim min max min max a 12.32 12.57 0.485 0.495 b 12.32 12.57 0.485 0.495 c 4.20 4.57 0.165 0.180 e 2.29 2.79 0.090 0.110 f 0.33 0.48 0.013 0.019 g 1.27 bsc 0.050 bsc h 0.66 0.81 0.026 0.032 j 0.51 0.020 k 0.64 0.025 r 11.43 11.58 0.450 0.456 u 11.43 11.58 0.450 0.456 v 1.07 1.21 0.042 0.048 w 1.07 1.21 0.042 0.048 x 1.07 1.42 0.042 0.056 t 0.50 0.020 z 2 o 10 o 2 o 10 o g1 10.42 10.92 0.410 0.430 k1 1.02 0.040 n otes: 1. datums ?l-, -m-, and ?n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum ?t-, seating plane. 3. dimensions r and u do not include mold flash. alowable mold flash is 0.010mm (0.250in.) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the packge bottom by up to 0.012mm (0.300in.). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be smaller than 0.025mm (0.635in.).
az10e111 az100e111 october 2001 * rev - 2 www.azmicrotek.com 6 arizona microtek, inc. reserves the right to change circuitry a nd specifications at any time without prior notice. arizona mic rotek, inc. makes no warranty, representation or guarantee regarding the suitability of its pr oducts for any particul ar purpose, nor does a rizona microtek, inc. assume any liability arising out of the applica tion or use of any product or ci rcuit and specifically disclaims any and all liability, including without limitation special, consequential or in cidental damages. arizona mi crotek, inc. does not convey a ny license rights nor the rights of others. arizona microtek, inc. products are not designed, intended or authorized for use as component s in systems intended to support or sustain life, or for any other applica tion in which the failure of the arizona microtek, inc. product could create a situation where personal injury or death may occur. should buye r purchase or use arizona microtek, inc. products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold arizona mi crotek, inc. and its officers, employees, subs idiaries, affiliates, and distributor s harmless against all claims, costs, damages, and expenses, and reasonable a ttorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that arizona microtek, inc. was negligent regarding the design or manufacture of the part.
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